Method of fabricating triple polysilicon non-volatile memory cells

ABSTRACT

A contact-less array of self-aligned, triple polysilicon, source side injection, nonvolatile memory cells with metal-overlaid wordlines includes: a plurality of pairs of stacks of first, second and third layer polysilicon arrange in rows; a drain region between the two stacks in each pair of polysilicon stacks, the drain regions being self-aligned to the edges of the two stacks; and a source region between each of the two adjacent pairs of polysilicon stacks, the source regions being self-aligned to side-wall spacers formed adjacent to edges of the polysilicon stacks such that each source region is laterally spaced an equal distance from the edges of the two stacks of polysilicon between which the source region is located.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates to semiconductor non-volatilememory technology and more particularly to a structure of and a methodfor producing a contactless array of self-aligned, triple polysilicon,source-side injection, flash memory cells.

[0003] 2. Description of Related Art

[0004] FIGS. 1A-1C show different perspectives of a contact-less arrayof triple-polysilicon, source side injection, flash EPROM cellsdisclosed by Ma et al. in U.S. Pat. No. 5,280,446 issued Jan. 18, 1994,and incorporated herein by reference.

[0005] In FIG. 1A, each cell includes a drain diffusion 40, a sourcediffusion 50, a floating gate 10 (first layer poly), a control gate 20(second layer poly), and a select gate 30 (third layer poly). Thefloating gate 10 and the control gate 20 extend over a first portion L₁of the channel region L. The source diffusion 50 is laterally spaced adistance L₂ from the floating gate 10. L₂ forms a second portion of thechannel region L. The drain diffusion 40 is self-aligned with the stackof floating gate 10 and control gate 20. This cell structure is commonlyreferred to as “split gate” because it merges two serially connectedtransistors (i.e., the select gate transistor and the floating gatetransistor) into a single memory cell. The select gate 30 extends in adirection which is perpendicular to a drain extension, and runs over thedrain diffusion 40, the control gate 20, the portion L₂ of the channelregion L, and the source diffusion 50 of every cell in a row of suchcells.

[0006] A layout diagram of two rows of memory cells, each rowcorresponding to the cross section view of FIG. 1A, is shown in FIG. 1B.The floating gates are shown as the cross hatched regions 10; the draindiffusions are connected together forming a column 40 (drain bitline);the source diffusions are connected together forming another bitlinecolumn 50 (source bitline); the control gates are connected togetherforming yet another column 20 (polysilicon line); and the select gatesare connected together forming a row 30 (wordline) perpendicular to thecolumns.

[0007] The drain and source diffusion bitlines are strapped with metallines (not shown) to minimize the resistance associated with thediffusion bitlines. This is necessary in order to achieve the desiredread and programming characteristics. Contacts are used to strap thediffusion bitlines with metal (e.g., one contact may be used every 64 or128 cells). The number of contacts used along these bitlines depends onthe technology and performance requirements. This type of arrayarchitecture is commonly referred to as a contact-less array because,unlike the conventional common source array architecture (wherein onecontact is required for every two cells), the contact design rules donot limit the size of the cell. Therefore, scaling of the memory cell insuch contact-less array architecture is made easier.

[0008]FIG. 1C is a circuit diagram of two rows and six columns of memorycells corresponding to the cross section and layout views in FIGS. 1Aand 1B, respectively. This diagram shows the mirror image formation ofthe memory cells along each row, i.e., every two adjacent memory cellsalong a row are mirror images of one another.

[0009] The read, programming and erase operations of this arrayarchitecture are described in detail in the above-mentioned '446 patent.Suffice it to state that programming is achieved through source sideinjection, and erasing is achieved through tunneling between thefloating gate and the drain diffusion.

[0010] This flash EPROM approach possesses a number of drawbacks. First,during the deposition and definition of select gates 30 (FIGS. 1A and1B), poly stringers form between adjacent rows of select gates 30,causing electrical shorts between them. The stringers form because theselect gates 30 overlay a tall stack of first and second layer poly(approximately 4,000 Å high), and the conventional select gate etch,used in both the periphery and the array regions, does not fully removethe third layer poly in the array region, leaving behind poly stringers.Thus, additional etching in the array region is needed. Since the thirdlayer poly in the periphery region does not require the over etching, anadditional masking step is needed.

[0011] Second, the second layer poly (control gate 20) can not receivetungsten silicide (WSi₂) due to the step height of the poly stack.Incorporating a tungsten silicide layer in the already tall stack oftriple poly only exacerbates the problems associated with this stack,such as the stringers. However, without tungsten silicide, the RC timeconstant associated with control gates 20 is large, causing slowprogramming and erase functions.

[0012] Third, in high density memory devices, due to the typically largeRC time delay associated with the polysilicon wordlines (select gates30), strapping of the polysilicon wordlines with metal is required inorder to achieve reasonable address access time. Such strapping requiresdrop contacts for making electrical contact between the poly wordlineand the metal strap. The drop contacts result in larger array area.

[0013] Fourth, during the select gate oxidation step wherein the selectgate oxide is formed, a phenomenon, commonly referred to as “cusping”,occurs which results in a number of reliability problems. FIGS. 2A-2Dillustrate this phenomenon. FIG. 2A shows the cross section of a stackof first layer polysilicon 10 (poly 1) and second layer polysilicon 20(poly 2), the tunnel oxide 80 under poly 1, and the overlying layer ofoxide 70. In FIG. 2B, the oxide layer 70 is removed through a dip offprocess, which as shown, results in removal of portions 81 of the tunneloxide 80 under the outside edges of poly 1. In FIG. 2C, the gateoxidation step wherein gate oxide 90 is grown over the entire cell,results in raising of the outside edges of both poly 1 and poly 2. Thisphenomenon is commonly referred to as “smiling poly”. When the thirdlayer of poly 30 (poly 3) is deposited over the gate oxide 90, as shownin FIG. 2D, the contours of poly 1 result in “cusping” of poly 3 (i.e.,poly 3 is pinched in the areas under the two ends of poly 1 as shown inthe encircled region 82).

[0014] Cusping of poly 3 results in a number of reliability problems.First, the raised edges of poly 1 result in thicker tunnel oxide underthese edges. This in turn results in slower erase since erase occursthrough the tunnel oxide region between poly 1 and the drain diffusion40 in the area marked as 82. Second, the oxide under the edges of poly 1is formed from oxidized poly 1, which is a poor quality oxide. Suchoxide possesses many trap sites which degrade the cyclingcharacteristics of the device. Third, the cusping of poly 3 causesdevice failures due to charge loss during such reliability procedures ashigh voltage, high temperature dynamic burn-in cycles. Fourth, thecusping causes early retention failures during retention bake becausethe sharp corner of the cusp results in high fields.

SUMMARY

[0015] In accordance with the present invention, a fully self-aligned,triple polysilicon, source side injection, nonvolatile memory cellsuitable for use in a contact-less array of such cells wherein wordlinesare overlaid with metal, as well as a method for producing the same isprovided.

[0016] The following outlines one set of process steps for producingsuch contact-less array of nonvolatile memory cells in a siliconsubstrate: (a) a plurality of pairs of stacks of first and second layerpolysilicon are formed along a row over the substrate; (b) a drainregion is then formed in the substrate between the two stacks in eachpair of polysilicon stacks, each drain region being self-aligned to theedges of the two stacks; (c) side-wall spacers are then formed adjacentto edges of each polysilicon stack; and (d) a source region is thenformed in the substrate between each of two adjacent pairs ofpolysilicon stacks, the source region being self-aligned to the edges ofthe oxide spacers.

[0017] In one embodiment, a composite layer of, in the order from bottomto top, HTO-Nitride-Polysilicon (ONP) is formed over the arrayimmediately after step (b). After step (d), the array surface isplanarized using an insulating material, and then a trench is createdover the row of cells by selectively removing the insulating materialfrom over the row of cells. Next, the ONP composite layer is convertedto an ONO composite layer, and the ONO composite layer is thenanisotropically etched to form side-wall spacers adjacent to the edgesof the polysilicon stacks. Select gate oxide is then grown over the rowof cells, after which a third layer of polysilicon is formed over theselect gate oxide. Finally, the third layer of polysilicon is overlaidwith a layer of metal.

[0018] In yet another embodiment, a contact-less array of nonvolatilememory cells includes: a row of pairs of stacks of first and secondpolysilicon layers over a silicon substrate, the first polysilicon layerbeing insulated from the substrate, and the second polysilicon layerbeing insulated from the first polysilicon layer; a drain region in thesubstrate between the two stacks in each pair of polysilicon stacks, thedrain region being aligned to the edges of the two stacks; a sourceregion in the substrate between two adjacent pairs of polysiliconstacks, the source region being self-aligned to side-wall spacers formedadjacent to edges of the polysilicon stacks such that the source regionis laterally spaced an equal distance from the edges of the two stacksof polysilicon between which the source region is located; and a thirdlayer of polysilicon over but insulated from the row of polysiliconstacks and the silicon substrate, the third layer of polysilicon forminga wordline in the array.

[0019] One feature of the present invention is that the polysiliconlayer in the ONP composite layer helps achieve a self-aligned sourceregion by facilitating the use of oxide spacers in the source formationstep.

[0020] Another feature is that a fully planarized array is obtained byutilizing the ONP composite layer in combination with the CMPtechnology, thereby eliminating all complications typical tonon-planarized cell technologies, such as (i) the stringer problemdiscussed above and (ii) the inability to form tungsten polycide overthe control gate due to the tall height of the polysilicon stack.

[0021] Yet another feature is that the “ONO spacers” adjacent each stackof polysilicon prevent cusping of the third layer polysilicon therebyeliminating reliability problems associated with such cusping.

[0022] Yet another feature is that polysilicon wordlines are strappedwith metal without use of drop contacts, thereby minimizing the wordlineRC time delay without any area penalty.

[0023] Yet another feature is that the processing steps of the presentinvention can easily be integrated with conventional ETOX processes,thereby facilitating transporting these process steps to anymanufacturing foundry using the ETOX process.

[0024] These and other features and advantages of the present inventionwill become more apparent from the following description and theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1A is a cross section view of a row of prior art triplepolysilicon, source side injection, flash EPROM cells.

[0026]FIG. 1B is a layout diagram of two rows of flash EPROM cells, eachrow corresponding to the row of cells in FIG. 1A.

[0027]FIG. 1C is a circuit representation of the two rows of flash EPROMcells in FIG. 1B.

[0028] FIGS. 2A-2D show the process steps leading to “cusping” of theselect gate 30.

[0029] FIGS. 3A-3E and 3G-3L are cross section views of a sample portionof a row of memory cells at succeeding stages of fabrication inaccordance with one embodiment of the present invention.

[0030]FIG. 3F is a layout diagram corresponding to the process stepwherein trenches 210 are formed in the oxide.

[0031] FIGS. 4A-4D show in more detail the steps carried out in formingthe ONO spacers 600 in FIG. 3J.

[0032]FIG. 4E shows a more detailed cross section of a stack ofpolysilicon corresponding to any one of the six poly stacks in FIG. 3K.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0033] FIGS. 3A-3L show one embodiment of the present invention. Thesefigures depict the cross section views at succeeding stages offabricating a sample portion of a row of flash EPROM cells. These memorycells are split gate cells serially connected in mirror image formationalong each row in a contact-less array of such cells, similar to thatshown in FIG. 1C.

[0034]FIG. 3A shows a cross section of six polysilicon stacks S1-S6after the initial few processing steps. These stacks of poly are formedover the substrate 40 in accordance with the conventional ETOX process.Each stack includes the tunnel oxide 50, the first layer polysilicon 60(poly 1), the second layer polysilicon 70 (poly 2), and the dielectriclayer 80 (which typically comprises a composite layer ofoxide-nitride-oxide). Also, the poly 2 layer is overlaid with tungstensilicide (Wsi₂) not shown. In this and all subsequent figures, layer 70is presumed to include a layer of tungsten silicide. Finally, layer 70is overlaid with the oxide layer 90 which is High Temperature Oxide(HTO).

[0035] The poly stacks S1-S6 are spaced in a specific manner in order tofacilitate the mirror image formation of the split gate cells. As shown,the polysilicon stacks are formed in pairs wherein the distance betweenthe two stacks in each pair is smaller than the distance betweenadjacent pairs (e.g., the distance between stacks S1 and S2 is shorterthan the distance between stacks S2 and S3). In one embodiment thedistance between S2 and S3 is three times that between S1 and S2.

[0036] In FIG. 3B, an implant step is carried out to form the n+ buriedbitline drain diffusions 30. Photoresist layer 10 along with the polystacks are used to cover those areas of the substrate surface that arenot to receive the arsenic implant 20. The two stacks in each pair ofpoly stacks (e.g., stacks S1 and S2) define a window through whicharsenic 20 is implanted into the substrate 40. In this manner, the inneredges of adjacent stacks of ploy, such as S1 and S2, define the outerboundaries of the drain diffusions 30, hence the term self-aligned draindiffusions. Similar to conventional virtual ground arrays, bitlinediffusions 30 are shared by two adjacent memory cells. However, unlikeconventional virtual ground arrays wherein each diffusion my serve asboth a drain and a source diffusion, diffusions 30 serve only as draindiffusions.

[0037] In FIG. 3C, a composite layer of ONP (Oxide-Nitride-Polysilicon)100 is deposited over the entire array, and then an undoped layer of CVDoxide 110 is deposited over the ONP composite layer 100. The ONPcomposite layer 100 consists of, in the order from bottom layer to toplayer, 100 Å of High Temperature Oxide (HTO) or thermal oxide, 150 Å ofNitride and 100-500 Å of intrinsic polysilicon. For this embodiment, athickness of 400 Å is best suited for the intrinsic poly layer. Theintrinsic poly serves as a buffer layer, protecting the underlying ON(Oxide-Nitride) composite layer from exposure to subsequent processingsteps.

[0038] The undoped CVD oxide layer 110 may be TEOS with a thickness inthe range of 4,000-10,000 Å. In FIG. 3D, the oxide layer 110 isanisotropically etched back until the top buffer polysilicon layer ofthe ONP composite layer 100 is first exposed. In this manner, oxidespacers 140 are formed. Note that oxide spacers 140 completely fill theopenings over the drain diffusions 30 (e.g., between stacks S1 and S2)due to the narrow width of the openings. But the oxide spacers 140create a window in the opening between two adjacent pairs of polysiliconstacks (e.g., between stacks S2 and S3).

[0039] Next, self-aligned n+ buried bitline source diffusions 120 areformed by implanting arsenic 130 through the windows formed by oxidespacers 140. In this manner, the edges of each pair of window-formingoxide spacers 140 define the boundaries of source diffusions 120, hencethe term self-aligned source diffusions. Drain regions 30 do not receivethe implant 130 since the openings directly over these regions arefilled with oxide. Similar to drain diffusions 30, each diffusion 120serves strictly as a source diffusion and is shared by two adjacentmemory cells along the wordline dimension.

[0040] The split gate configuration of each cell can now be recognizedin FIG. 3D even though the select gate is not yet present. For example,the fourth cell from the left comprises the poly stack S4, the draindiffusion 30 immediately to the left of stack S4, the source diffusion120 immediately to the right of stack S4, and the channel region 80between the two diffusion regions. As shown, the channel region 80,commonly referred to as L_(eff), is made up of a portion L₁ which isdirectly under the poly stack S4, and the remaining portion L₂. As inany split gate cell, this cell is made up of a floating gate transistor(represented by the L₁ portion of the channel region 80) in series witha select gate transistor (represented by the L₂ portion of the channelregion 80).

[0041] The thickness selected for the oxide layer 110 in FIG. 3C impactsthe length of the channel region 80, and more specifically the portionL₂. Generally, a thicker oxide layer 110 results in a longer L₂.Therefore, depending upon the desired L₂, an appropriate thickness isselected for the oxide layer 110. The thickness of the oxide layer 110is in the range of 5000 Å-7000 Å, and the preferred thickness for thisembodiment is 7000 Å.

[0042] In carrying out the steps depicted by FIGS. 3C and 3D, twoparameters which effect the performance of the memory cell are takeninto account: (1) the oxide spacer etch back uniformity across thewafer, and (2) the oxide to poly selectivity. The oxide spacer etch backuniformity is typically about ±10% (a total of 20%) across the wafer.This means that in etching back, for example, 7,000 Å of oxide 110, whenthe first exposed buffer poly surface is detected, other areas on thewafer may have as much as 1,400 Å (20% of 7,000 Å) of oxide 110remaining. Therefore, additional etching is required to remove theremaining oxide.

[0043] The additional etching of the oxide 110 however, results inremoval of a certain amount of the buffer poly layer in those areaswhere the buffer poly is exposed earlier. The oxide to poly selectivityis typically about 30:1, which means for every 30 Å of oxide that isetched back, 1 Å of polysilicon is lost. Accordingly, in etching backthe remaining 1,400 Å of HTO in the above example, approximately 120 Åof the buffer poly (30% of 400 Å) is lost in those areas where thebuffer poly is first exposed. Note that the thickness of the buffer polylayer must be carefully selected to take into account such losses inthickness.

[0044] Accordingly, the buffer poly layer is used to indicate when tostop etching the oxide 110, and also to “buffer” or protect theunderlying ON composite layer, which as will be seen, forms part of theinsulating layer between the second and third poly layers. A defect-freeinsulating layer minimizes the risk of oxide damage during deviceoperations in which high voltage is applied across poly 2 and poly 3.

[0045] In accordance with the above steps, both the source diffusions120 and the drain diffusions 30 are formed in a fully self-alignedmanner. As such, L_(eff) variations across the wafer due tomisalignments are minimized resulting in a more predictable process.More importantly, scaling of such memory cell is achieved more easily.

[0046] Next, through a two step process, the surface of the array regionis planarized, as shown in FIG. 3E. First, 10,000 Å-15,000 Å of undopedoxide is deposited over the entire array through a Chemical VaporDeposition (CVD) step. Second, using the well known technique ofChemical Mechanical Polish (CMP), or other planarization techniques suchas resist etch back, the entire surface area of the array is planarized.These two steps, in effect, result in filling the cavities in the arraywith Oxide 200 thereby producing an even surface. After completion ofthe two steps, the oxide thickness, indicated as t_(ox1) in FIG. 3E, isin the range of 5000 Å-7000 Å. It is not necessary to remove the oxidespacers 140 prior to carrying out these two steps. However, the spacers140 may be removed through a Hydride Florid (HF) dip etching step ifdesired. Note that the buffer poly is unaffected by this etching processbecause, wet etch does not attack polysilicon.

[0047] With a planarized array, a select gate mask is used toselectively etch the oxide 200 such that trenches are created in theplanarized array directly over the rows of memory cells. FIG. 3F is alayout diagram of two rows of memory cells wherein a select gate mask(shown as the large cross hatched area 700) is used to carry out thisstep. The control gates are shown as regions 70 extending in thevertical dimension; the n+ buried source diffusions are shown as regions120 extending in the vertical dimension forming dedicated sourcebitlines; the n+ buried drain diffusions (the regions in between twoadjacent control gates) are shown as regions 30 extending in thevertical dimension forming dedicated drain bitlines; and the floatinggates are shown as the cross hatched areas 60 underneath the controlgates 70.

[0048] Photoresist is used as the select gate mask 700, and similar tocontact hole definition, the photoresist 700 covers the entire arrayother than areas 210 wherein the third layer of poly (select gate) islater deposited. Through a dry etch step, the oxide exposed in areas 210(i.e., oxide 200 in FIG. 3E) is etched back until the buffer polydirectly over the stacks of poly is first exposed. At that point,additional etching is carried out to remove the oxide in areas betweenadjacent stacks of poly. In this manner trenches are created (defined byregions 210) in the planarized surface of the array. As shown, trenches210 extend in the horizontal dimension over the stacks of first andsecond layer poly.

[0049]FIGS. 3G and 3H show cross sections of the FIG. 3F array acrossrespective lines A-A and B-B after the oxide etch and removal of thephotoresist mask 700. FIG. 3G corresponds to the trench area 210 in FIG.3E, and shows the oxide previously used in planarizing the array (i.e.,oxide 200 in FIG. 3E) being absent. FIG. 3H shows the oxide 200 to beintact in the areas between the trenches 210 where photoresist 700covered the array.

[0050] In this step, as in the source diffusion definition step, thebuffer poly layer of the ONP composite layer 100 is used to control theetching of the oxide in the trench regions 210. As indicated above, inthe trench regions 210, those portions of the ONP composite layerdirectly over the poly stacks are exposed prior to the portions in theareas between the stacks of poly. As a result, this etching step willresult in removal of a certain amount of the buffer poly directly overthe stacks of poly. The thickness of the buffer poly need to be properlyselected to account for such losses.

[0051] In determining the extent of buffer poly removed in this step,the above described two parameters, namely, oxide etch back uniformityof ±10%, and oxide to poly selectivity of 30 to 1, are used. Assumingt_(ox2) is 4000 Å, etching the 4000 Å in the between the poly stack willresult in removal of 133 Å of the buffer poly in the areas directly overthe poly stacks. Thus, in these areas, of the original 400 Å of bufferpoly, approximately 147 Å remains, given that 120 Å was removed in theprevious oxide etch step.

[0052] Next, the ONP composite layer is converted to an ONO compositelayer by oxidizing the top buffer poly layer through a wet oxidationcycle. By oxidizing the conductive buffer polysilicon layer, it isrendered non-conductive thereby eliminating the potential for shortingthe select gates which are later deposited on top of the ONO compositelayer. Layer 500 in FIG. 3I is intended to show an oxidized ONPcomposite layer, or simply the ONO composite layer.

[0053] This oxidation step results in a top oxide layer having athickness approximately twice that of the buffer poly layer.Accordingly, in the above example, the 147 Å and 280 Å of buffer poly inthe areas over the poly stacks and between the poly stacks,respectively, convert to 294 Å and 560 Å of oxide, respectively. Notethat this oxidation cycle also oxidizes the buffer poly layer in regionsother than trenches 210 (i.e., regions exemplified by line B-B in FIG.3F) despite the thick oxide layer covering the buffer poly in theseregions.

[0054] In FIG. 3J, the ONO composite layer 500 is anisotropically etchedto form the ONO spacers 600 along the side walls of the poly stacks. TheONO spacers 600 may have a thickness in the range of 400-1,500 Å at thebottom. A thickness greater than 1,500 Å reduces the read andprogramming currents of the cell and thus is undesirable.

[0055] FIGS. 4A-4D show in more detail the steps carried out in formingthe ONO spacers 600 (FIG. 3J). FIG. 4A shows a stack of polysiliconwhich corresponds to any one of the six poly stacks in FIG. 3I. Thethree layers forming the ONO composite layer 500 (FIG. 3I) are shown inFIG. 4A as Oxide layer 800, nitride layer 801, and oxide layer 802. InFIG. 4B, the top oxide layer 802 is anisotropically etched resulting inthe formation of the oxide spacers 803. In FIG. 4C, the nitride layer801 (FIG. 4B) is etched, resulting in removal of all the nitride otherthan the nitride “feet” 804 under oxide spacers 803. In FIG. 4D, theoxide layer 800 (FIG. 4C) is etched using a wet dip process, resultingin the undercuts 806 under the nitride feet 804. In the absence of theONO spacers (which is made up of the oxide 800, the nitride foot 804,and the oxide 803), similar undercuts would occur under poly 1 whichultimately would result in cusping of poly 1. The ONO spacers alsoprevent cusping of poly 1 during the poly 3 (select gate) oxidationcycle for similar reasons. Further, the nitride feet 804 protect theedges of the poly stacks from subsequent processing steps.

[0056] In FIG. 3K, through a thermal oxidation cycle, select gate oxide610 is formed over the row of poly stacks. FIG. 4E shows in more detaila stack of polysilicon corresponding to any one of the six poly stacksin FIG. 3K. As shown, oxide 610 creates a continuous and smooth surfaceover which poly 3 is late deposited. The thickness of the oxide 610 isin the range of 70 Å to 200 Å, with a preferred thickness ofapproximately 80 Å. Note, that the oxidation cycle does not result ingrowth of oxide in the areas directly over the nitride feet 804 sincenitride prevents growth of oxide.

[0057] In an alternate embodiment, a thin ONO composite layer, in therange of 70-200 Å, is deposited as the select gate dielectric 610.Depositing of the ONO composite layer does not require the use of thehigh temperature cycle (600° C.-900° C.) associated with the highthermal oxidation cycle. Such high temperature cycles adversely effectthe source/drain diffusions in the periphery and the array by causingexcessive side diffusion. This results in L_(eff) becoming shorter thanthe target L_(eff).

[0058] In FIG. 3L, a third layer of poly 710 (poly 3), having athickness of approximately 8,000 Å, is deposited over the array usingthe Low Pressure Chemical Vapor Deposition (LPCVD) process. The poly 3is subsequently doped with phosphorous and then etched back withoutusing a photoresist mask. The poly 3 is uniformly etched back until thefirst underlying layer, namely, oxide 200 in FIG. 3H, is first exposed.Once the oxide 200 is exposed, additional etching is carried out (e.g.another 10% removal of poly 3) to ensure that the poly 3 is fullyremoved from over the array areas covered with oxide 200. Because of thenarrow width of the trench area 210 (in the range of 0.25-0.5 μm), thetrench 210 remains filled with poly 3 after the etch step. In thismanner, the poly 3 in trenches 210 form select gates or wordlines 710which run across the array in the horizontal direction.

[0059] With poly 2 forming the control gate of the peripherytransistors, next, contact holes are formed in the periphery regionwhile the array region is covered with photoresist (this step is notshown). The photoresist is then removed from over the array and Metal 1is deposited over both the periphery and array regions using theconventional metal sputtering process. The deposited metal 1 issubsequently defined through a metal 1 masking step in both the arrayand the periphery regions (this step is also not shown). In this manner,contact is made between the poly 3 and the overlying metal 1 withoutusing any contact holes. Three advantages are realized with suchstructure: (1) the RC time delay associated with poly wordlines issignificantly reduced, (2) a smaller array size is achieved because themetal plus contact pitch associated with the conventional method ofmaking contact between poly 3 and metal is reduced to solely a metalpitch, and (3) a more misalignment tolerant process is achieved sincethe contact between metal 1 and poly 3 is made without use of a contacthole (i.e., contact is made by simply overlaying poly 3 with metal 1providing for a greater metal 1 misalignment tolerance with respect topoly 3).

[0060] In contact-less arrays, such as that of the present invention,the source and drain diffusion bitlines, which extend across the array,are strapped with metal to reduce the large resistance associated withsuch diffusion lines. Metal 2 and contacts may be used to strap thedrain and source diffusion bitlines. Conventional process steps arecarried out to implement this portion of the fabrication process.

[0061] The processing steps depicted by FIGS. 3B-3L collectivelyrepresent a flash process module which can easily be integrated with anyconventional ETOX process, thereby facilitating transporting theseprocess steps to any manufacturing foundry using the ETOX process.

[0062] The above description of the present invention is intended to beillustrative and not limiting. The invention is further intended toinclude all variations and modifications falling within the scope of theappended claims.

What is claimed is:
 1. A method of fabricating an array of non-volatilememory cells in a silicon substrate, the method comprising: (A) formingover the substrate a plurality of pairs of stacks of first and secondlayer polysilicon along a row, the first layer being insulated from thesubstrate, and the second layer being insulated from the first layer;(B) forming in the substrate a drain region between the two stacks ineach pair of polysilicon stacks, each drain region being self-aligned tothe edges of the two stacks between which the drain region is formed;(C) forming side-wall spacers adjacent to edges of each polysiliconstack; and (D) forming in the substrate a source region between each oftwo adjacent pairs of polysilicon stacks, each source region beingself-aligned to the edges of the oxide spacers.
 2. The method of claim 1wherein the array is a contact-less array.
 3. The method of claim 2further comprising: (E) forming a composite layer of, in the order frombottom to top, HTO-Nitride-Polysilicon (ONP) over the array of memorycells immediately after step (B).
 4. The method of claim 3 furthercomprising: (F) planarizing the surface area of the array after step (D)using an insulating material.
 5. The method of claim 4 furthercomprising: (G) selectively removing the insulating material from overthe row of cells after step (F) thereby creating a trench directly overthe row of cells.
 6. The method of claim 5 further comprising: (H)converting the ONP composite layer to ONO composite layer after step(G).
 7. The method of claim 6 further comprising: (I) anisotropicallyetching the ONO composite layer to form ONO side-wall spacers adjacentto edges of the polysilicon stacks after step (H).
 8. The method ofclaim 7 further comprising: (J) growing select gate oxide over the rowof polysilicon stacks after step (I).
 9. The method of claim 8 furthercomprising: (K) forming a third layer of polysilicon over the row ofpolysilicon stacks after step (J), the third layer of polysiliconforming a wordline in the array.
 10. The method of claim 9 furthercomprising: (L) over laying the third layer of polysilicon with a layerof metal.
 11. The method of claim 10 wherein the first layer ofpolysilicon forms the floating gate, the second layer of polysiliconforms the control gate, and the third layer of polysilicon forms theselect gate.
 12. The method of claim 10 wherein step (A) furthercomprises overlaying the second layer polysilicon with tungstensilicide.
 13. The method of claim 10 wherein the side-wall spacers instep (C) are from silicon dioxide.
 14. The method of claim 13 whereinthe side-wall spacers in step (C) are created by anisotropically etchinga layer of oxide.
 15. The method of claim 14 wherein step (C) causes thespace between the two stacks in each pair of polysilicon stacks to fillwith oxide.
 16. The method of claim 10 wherein the distance between twoadjacent pairs of polysilicon stacks is greater than the distancebetween the two stacks in each pair of polysilicon stacks.
 17. Themethod of claim 16 wherein the distance between two adjacent pairs ofpolysilicon stacks is three times the distance between the two stacks ineach pair of polysilicon stacks.
 18. The method of claim 10 wherein thesource region is laterally spaced an equal distance from the edges ofthe two stacks of polysilicon between which the source region is formed.19. The method of claim 10 wherein step (B) comprises: (M) covering thesilicon substrate regions between adjacent pairs of polysilicon stackswith photoresist; and (N) implanting Arsenic into the exposed siliconsubstrate regions.
 20. The method of claim 10 wherein step (J) iscarried out using a thermal oxidation process.
 21. The method of claim10 wherein the select gate oxide comprises a thin layer of ONO compositelayer.
 22. The method of claim 10 wherein step (H) is carried out byoxidizing the conductive polysilicon layer of the ONP composite layer.23. The method of claim 10 wherein step (K) is carried out by uniformlyetching back a third layer of polysilicon deposited over the entirearray without using a photoresist mask.
 24. The method of claim 10wherein step (A) is carried out in accordance with conventional ETOXprocess.
 25. The method of claim 10 wherein the Chemical MechanicalPolish (CMP) technique or the resist etch back process is used toplanarize the array.
 26. The method of claim 10 wherein the memory cellsare split gate cells and every two adjacent split gate cells along therow are mirror images of one another.
 27. A contact-less array ofnon-volatile memory cells comprising: a row of pairs of stacks of firstand second polysilicon layers over a silicon substrate, the first layerpolysilicon being insulated from the substrate, and the second layerpolysilicon being insulated from the first layer polysilicon; a drainregion in the substrate between the two stacks in each pair ofpolysilicon stacks, the drain region being self-aligned to the edges ofthe two stacks; a source region in the substrate between two adjacentpairs of polysilicon stacks, the source region being self-aligned toside-wall spacers formed adjacent to edges of the polysilicon stacks,such that the source region is laterally spaced an equal distance fromthe edges of the two stacks of polysilicon between which the sourceregion is located; and a third layer of polysilicon over but insulatedfrom the polysilicon stacks, the third layer of polysilicon forming awordline in the array.
 28. The array of claim 27 further comprising anONO side-wall spacer adjacent to each edge of the stacks of polysiliconfor insulating the side-walls of each polysilicon stack from the thirdlayer polysilicon.
 29. The array of claim 28 wherein the distancebetween two adjacent pairs of polysilicon stacks is greater than thedistance between the two stacks in each pair of polysilicon stacks. 30.The array of claim 29 wherein the memory cells are split gate cells andevery two adjacent split gate cells along the row are mirror images ofone another.
 31. The array of claim 29 wherein the distance between twoadjacent pairs of polysilicon stacks is three times the distance betweenthe two stacks in each pair of polysilicon stacks.
 32. The array ofclaim 29 further comprising a layer of metal overlying the third layerof polysilicon.
 33. The array of claim 32 further comprising a layer oftungsten silicide overlying the second layer of polysilicon.
 34. Thearray of claim 29 wherein the insulating layer between the second andthird layer polysilicon comprises a thin layer of oxide-nitride-oxide(ONO) composite layer.
 35. The array of claim 29 wherein the pairs ofstacks of first and second layer of polysilicon are formed in accordancewith conventional ETOX process.
 36. The array of claim 29 wherein thedrain region is formed by covering the silicon substrate regions betweenadjacent pairs of polysilicon stacks with photoresist and implantingArsenic into the exposed silicon substrate regions.
 37. The array ofclaim 29 wherein the source region is formed by implanting Arsenicthrough a window formed by oxide side-wall spacers temporarily formedadjacent to each polysilicon stack whereby the source region isself-aligned to the side-wall spacers.
 38. The array of claim 37 whereina composite layer of, in the order from bottom to top,HTO-Nitride-Polysilicon (ONP) is formed between the oxide side-wallspacers and the stacks of polysilicon prior to source region formation.39. The array of claim 38 wherein the top polysilicon layer in the ONPcomposite layer is rendered non-conductive before deposition of thethird layer polysilicon.
 40. The array of claim 39 wherein the toppolysilicon layer in the ONP composite layer is rendered non-conductiveby oxidizing the polysilicon layer.
 41. The array of claim 29 whereinthe array of memory cells is planarized before the third layer ofpolysilicon is deposited.
 42. The array of claim 41 wherein the wordlineis formed by depositing the third layer of polysilicon in a trenchformed in the planarized array over the row of polysilicon stacks. 43.The array of claim 41 wherein the Chemical Mechanical Polish (CMP)technique or the resist etch back process is used to planarize thearray.
 44. The method of fabricating an array of non-volatile memorycells in a silicon substrate, the method comprising: (A) forming overthe substrate three stacks S1, S2 and S3 of first and second polysiliconlayers along a row, the first layer being insulated from the substrate,and the second layer being insulated from the first layer; (B) formingin the substrate a drain region between the stacks S1 and S2, the drainregion being self-aligned to the edges of the stacks S1 and S2; (C)forming side-wall spacers adjacent to edges of each polysilicon stack;and (D) forming in the substrate a source region between the stacks S2and S3, the source region being self-aligned to the edges of the oxidespacers.
 45. The method of claim 44 wherein the array is a contact-lessarray.
 46. The method of claim 45 further comprising: (E) forming acomposite layer of, in the order from bottom to top,HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediatelyafter step (B).
 47. The method of claim 46 further comprising: (F)converting the ONP composite layer to ONO composite layer after step(D); (G) anisotropically etching the ONO composite layer to form ONOside-wall spacers adjacent to edges of the polysilicon stacks; and (H)growing select gate oxide over the row of polysilicon stacks.
 48. Themethod of claim 47 further comprising: (I) forming a third layer ofpolysilicon over the row of polysilicon stacks after step (H), the thirdlayer of polysilicon forming a wordline in the array; and (J) overlyingthe third layer of polysilicon with a layer of metal.
 49. The method ofclaim 44 wherein step (B) comprises: (K) covering the silicon substrateregion between stacks S2 and S3 with photoresist; and (L) implantingArsenic whereby drain regions are formed in the silicon substrate regionbetween stacks S1 and S2.
 50. The method of claim 48 wherein step (A) iscarried out in accordance with conventional ETOX process.
 51. The methodof claim 45 wherein the distance between the stacks S2 and S3 is greaterthan the distance between the stacks S1 and S2.
 52. The method of claim45 wherein the distance between the S2 and S3 is three times thedistance between the stacks S1 and S2.
 53. A Contact-less array ofnon-volatile memory cells comprising: three stacks S1, S2 and S3 offirst and second polysilicon layers over a silicon substrate along arow, the first layer polysilicon being insulated from the substrate, andthe second layer polysilicon being insulated from the first layerpolysilicon; a drain region in the substrate between the stacks S1 andS2, the drain region being self-aligned to the edges of the stacks S1and S2; a source region in the substrate between the stacks S2 and S3,the source region being self-aligned to side-wall spacers formedadjacent to edges of the stacks S2 and S3, such that the source regionis laterally spaced an equal distance from the edges of the stacks S2and S3; and a third layer of polysilicon over but insulated from thepolysilicon stacks, the third layer of polysilicon forming a wordline inthe array.
 54. The array of claim 53 further comprising an ONO side-wallspacer adjacent to each edge of the polysilicon stacks for insulatingthe side-walls of each polysilicon stack from the third layerpolysilicon.
 55. The array of claim 53 wherein the distance between thestacks S2 and S3 is greater than the distance between the stacks S1 andS2.
 56. The array of claim 53 wherein the distance between the stacks S2and S3 is three times the distance between the stacks S1 and S2.
 57. Thearray of claim 55 wherein the memory cells are split gate cells andevery two adjacent split gate cells along the row are mirror images ofone another.
 58. A method of fabricating a non-volatile memory cell in asilicon substrate, the method comprising: (A) Forming over the substratea stack of first and second polysilicon layers, the first layer beinginsulated from the substrate, and the second layer being insulated fromthe first layer; and (B) Forming a layer of nitride adjacent the edgesof the stack for protecting the edges of the stack, the nitride layerbeing insulated from the edges of the stack.
 59. The method of claim 58wherein step (B) further comprises: (C) depositing a composite layer of,in the order from bottom to top, oxide-nitride-oxide (ONO) over thememory cell; (D) anisotropically etching the top oxide layer of the ONOcomposite layer; and (E) etching the nitride.
 60. The method of claim 59wherein step (B) further comprises: (E) etching the bottom layer of theONO composite layer after step (E).
 61. A non-volatile memory cellcomprising: a stack of first and second polysilicon layers over asilicon substrate, the first layer being insulated from the substrate,and the second layer being insulated from the first layer; and a layerof nitride adjacent the edges of the stack for protecting the edges ofthe, the nitride layer being insulated from the edges of the stack. 62.The memory cell of claim 61 wherein the nitride layer forms the middlelayer of a composite layer of, in the order from bottom to top,oxide-nitride-oxide (ONO).
 63. The memory cell of claim 62 wherein theONO composite layer is in the form of spacers adjacent to the edges ofthe stack.